Hi, this is Ed working for Arm. We're going to cover today the Armv8-M Mainline programmers' model. Before we begin, just to give you a very brief history of the M-Profile architecture. It started off with the Armv7-M architecture, which you will find is used in processes like the Cortex-M3 and M4 processes and Cortex-M7 processor. After Armv7-M was designed and architected, Arm came out with another architecture flavor called Armv6-M, which was a smaller version of the Armv7-M architecture, it was like a subset. It had fewer 32-bit instructions and there were some cuts made in terms of the complexity of the architecture. In Armv8-M, rather than deciding to perhaps come up with two new numbers, and perhaps for example, Armv8-M and Armv9-M, what was decided was that there would be one version number Armv8-M and two variants of that architecture. A baseline variant, which would be alike to the Armv6-M architecture. That provides all of the essential features you'd expect from the architecture, and is implemented in some of the smaller lower power processor implementations like Cortex-M23. Then there is the mainline variant of the Armv8-M architecture, which is implemented in systems like Cortex-M33. This presentation and the entire course is focused a bit more on the mainline variant of the Arm architecture, but we'll try it to cover occasionally when we think it's interesting where mainline and baseline differ, and where some of the smaller implementations might vary compared with some of the larger, grander implementations. We have some learning objectives. The first one is to define the basic data types used by the Armv8-M architecture. We had also looked at the Arm register bank, so that's registers r0 through to r12, things like the stack pointer register (SP), the link register (LR), program counter (PC). We'll also cover some details on how the stack pointer, link register, and program counter are used by software and are expected to behave according to the architecture. We'll describe the different process of modes of operation, so that's handler mode and thread mode. Thread mode is entered our reset it, and handler mode is used for handling exceptions. We'll also explain the differences between privileged and unprivileged execution. We'll introduce the exception handling mechanism. We've got a whole topic, a whole module on exception handling, it is a huge feature of the M-profile architecture. There's lots and lots of details, lots of nitty-gritty details to go into. We will however, introduce it in this module, just because it's good to get a flavor of how that works. We'll do something similar for the Thumb instruction set. I say thumb instruction set, it's actually these days known as the T32 instruction set, so that's the official name you'll see in the architecture reference manual. Then the final thing we'll do is describe the common programming standards, such as the AAPCS. So this acronym stands for the Arm Architecture Procedure Call Standard. If you actually open up the document it's called, the Procedure Calls Standard for the Arm Architecture, but that's not very interesting. Anyway, the other standard that will have a little bit of a look into is CMSIS, specifically CMSIS-Core. The CMSIS here stands for the Cortex/Common Microcontroller Software Interface Standards. Standards like these make programming a Cortex-M processor a lot easier. Whether you're writing in C or assembly language.