In this video, you will learn how to test the code you write using an HDL simulator. How to evaluate the correctness of your design using waveform analysis. And how to control the simulator to examine the code and its output. Suppose for example, you had written this Verilog code to implement a 4-bit adder. How can you verify that the code is correct, short of building it in an FPGA? Fortunately, there exists a tool specifically for evaluating HDL code called a simulator. It will take Verilog code input file, check it for in report syntax errors. And then once those are resolved, compile the code to an RTL level model. And then can simulate the model by creating signal waveforms for every signal in the model. This is called a functional simulation, because it simulates the function of the gates, without including time delays in the gate models. Come, simulate with me. Let's simulate the Add4.v code in ModelSim. This file has been provided to you. Start ModelSim now and follow the steps as we simulate this code together. Let's start the student edition of ModelSim. When you start ModelSim, you should see this Welcome dialog box. Select Jumpstart to use ModelSim right away. In the next dialogue, select to Create a Project. Enter the name Add4 into the Project Name space. You'll need to copy the supplied Add4.v file to the Modeltech examples directory, which is shown in the project location here. Stop and do that now. Once you have Add4.v in the proper directory, then you want to go ahead and click OK here. You won't see this probably new project. And then you'll see a dialog box to Add items to the Project. We want to add an existing file. So we'll browse here. Take us back to that project directory. I'm going to select the Add4, open that, and I'll select OK. And we see that it shows up there, and so we can go ahead and close this dialog box. Now you see the project window in ModelSim. With the transcript window at the bottom. The transcript window shows tickle commands that execute as the tool is performing its functions. So click on Add4.v, so that is selected. Then at the top level menu click on Compile > Compile Selected. You should see the status is changed to a green checkmark here. And also you'll see a message saying that the compilation of that for was successful. Next, click on the Library tab. And you see a wide ranging list of libraries, including all the IEEE libraries that ModelSim provides for you. Click on the + in front of the work library to expand it. And there you'll find Add4 again. So you're going to right click on Add4 > Simulate to start the simulation. A number of new windows now appear, including the sim window on the left. The objects window in the upper centre, processes window in the mid centre. Transcript window is still below, and then on the right is the list and waveform window. The icon panes at the top may be in some disarray, if so you can move them to be contiguous. Stick them like so. We can simulate the adder by adding the port signals within the object window here by clicking on one, hitting Ctrl+A, opening up the waveform window and then just dragging all the symbols over to the waveform window. Now we have the signals here. Click on the + to expand all the buzzes, as you can see. All the signals that make up the buzz. Click on Cn, and then right click on it and select Force. Change the input signal here from a z to a 1. The input value next to the h, which is the symbol for the current radix, which is hex in this case. Click OK. Now do the same procedure to change Data1 to a 2. And Data2 to a 3. The input data is now set for simulation. It's been forced to a known quantity. And so now if you go to the top center here, there's a down arrow which you click on, in order to simulate for 100 nanosecond. And so the first 7 nanoseconds looks like this. You should see the wave forms for these signals are generated. And that the value of the output is 6. As we would expect, wait a minute, 2 plus 3, is that equal to 6? Why is it the value 5? This is supposed to be an adder. The addition of the carry bit up here, which we set to a 1 means we're adding 1, 2, and 3 and then therefore getting 6. So this is correct. So the adder is working, at least for this case. We need to run other cases, in order to test it fully. So go back now and change the value of Data1, force it to be 0. And change Data2, and force it to be an f. Now we can hit the run down arrow here and simulate for another 100 nanoseconds. And so we see that we get 0 for data 1 and f for data 2. And then the output is 0. So does 15 plus 0 plus 1 equal to 0? Yes, in this case, because 16 can't be represented in 4 bits, so we have a carryout, and we see that the carryout signal is a 1 now. We can change the Radx representation of Data2 by right clicking on it, selecting Radx, and we can change it say to Unsigned. And now that instead of an f we have a 15. We can change it again now to Decimal. And now it says it's a -1, because now this is a signed number. We can also change this to Binary, and we see we have all 1s in this case. We can undock the waveform window by clicking on the symbol on the upper left corner. And now we can expand this, make it bigger, add a cursor down here. Which gives us all the values at a particular point in time, and so on. So what we've learned now at this point is how to run the simulator manually. And this would appear to be a very tedious way to run a bunch of test cases. Later you'll learn how to use a program at Verilog called the Testbench, which will automatically generate input data for your simulations. This is generally the technique we would employ to run simulations that being the Testbench. In this video, you have learned how to test the code you write using HDL Simulator ModelSim. How to evaluate the correctness of your design using waveform analysis. And how to control the simulator to examine the code and its output. In this case of 4-bit adder using different number combinations to get good test coverage.
