Verilog for fun and profit (intro) - Basics of Verilog | Coursera

Verilog for fun and profit (intro)

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Universidad de Colorado en Boulder

Hardware Description Languages for FPGA Design

Universidad de Colorado en Boulder

4.4 (504 calificaciones)

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28 mil estudiantes inscritos

Curso 2 de 4 en FPGA Design for Embedded Systems Programa Especializado

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This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

Destrezas que aprenderás

Writing Code in Verilog, Simulating FPGA Designs, Designing FPGA Logic, Designing Test Benches, Writing code in VHDL

Reseñas

4.4 (504 calificaciones)

5 stars
58,92 %
4 stars
27,97 %
3 stars
6,94 %
2 stars
2,97 %
1 star
3,17 %

KK

4 de jun. de 2020

This is very good course , but i found some little missing details related to reading materials .

But this was really very helpful course for me as fresher .

KP

27 de oct. de 2020

I think this is a good start in learning how to write VHDL and Verilog.

I would like to see a next level course or recommendations for further writing code.

De la lección

Basics of Verilog

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

Verilog for fun and profit (intro)3:35

Your First Verilog phrase11:07

Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12:27

Verilog Statements and Operators16:15

Verilog Modules, Port Modes and Data Types10:56

Verilog Structure10:31

Testing with ModelSim5:48

Verilog Evaluation11:24

Impartido por:

Timothy Scherr
Senior Instructor and Professor of Engineering Practice
Benjamin Spriggs
Lecturer and Scholar of Engineering Practice

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