In this video, you will learn the basics of Verilog syntax, Verilog variable values and data types, and some suggested editors that can be used to create Verilog code. Many syntax rules are very similar between C and Verilog, Verilog kind of derived from C to a certain extent so that they make sense that some of these things are similar. If you're used to writing C code, then you'll become familiar with writing Verilog code much more quickly probably and you'll find it easier to learn perhaps than it was to learn VHDL. In Verilog, white space is ignored, comments are either started with a double slash or a slash asterisk similar as in C, identifiers are words for variables, function names, etc. They can begin with an underscore or a letter and can include letters, digits, and underscores and are case sensitive unlike VHDL which is not case sensitive. And so if you capitalize a particular variable name and then you have a non capitalized version of that, those are going to be two different variables within Verilog. It's important to choose distinctive identifiers so that your code will be as self-documenting as possible. Keywords can't be used as identifiers and some of the keywords you'll see are things like a sign, case, while, wire, reg, and, or, nand, and module, just to name a few. The number of keywords and capabilities have expanded as Verilog and then System Verilog was developed as shown on the next slide. So here we see that initially Verilog 1995, this is not an exhaustive list of all of the keywords, but it's a good number of them. And also there's some other capabilities and has the operators that were used so long in 1995. And then 2001 we added some additional keywords like generate, automatic, and a few others. And some other capabilities as well, they're listed here. Not a lot of changes in 2005, added uwire for example, but then when we get to System Verilog, a number of additional capabilities have been added, some with respect to design, others with respect to verification. So we see a lot of additional keywords like break, continue, return, and so on, some additional operators. The different types of functions that can be used and for verification assertions and expansions of lot of other kinds of capability within System Verilog. So depending on which version of Verilog you're using, you're going to have a different set of keywords, a different set of capabilities, and so on. So this is just a nice little table and give you an idea of what these are. Within the FPGA world, Verilog 2001 is supported by most vendors. Some of them support System Verilog, some do not, and usually they're a revision or two behind in their support of these languages. And you will see lots of modules written in older versions of Verilog as well as System Verilog, and so on, and mixed together within projects. So number of literals are expressed this way, it's kind of unique in Verilog. If you have a 3-bit number, you'll represent that 3-bit number and then in front of it you have a b for binary, a tick mark and then a 3 representing the number of bits that are in the 3-bit number. So that first number is a decimal number. And then that in general gets followed by the tick mark and then the base whatever happens to be and then the number representation in that base. So here we see, binary, a decimal, and then a hexadecimal number of various bit sizes. You can add an underscore within that number for improved readability to kind of separate out sections of the number. But the underscore gets ignored when it's actually being synthesized or simulated, so it doesn't have any effect on the number at all. This is convenient and helpful in trying to make the them more clear. So a Verilog variable can assume any of four basic values so you can have a 0, a 1, an x, or z, and that's it. There isn't a nine value type of logic like there is in VHDL. So you can have a 0 which represent 0 or false condition, a 1 which represents a logic 1 or 2 condition. A z which represents high impedance state and then an x which can be unknown, uninitialized, or can indicate that there's some contention between two drivers on a particular wire. Which can make it unknown in that case and that would indicate a problem. So x in the simulators is represented usually in red. So as you're doing a simulation if you see a lot of red that might be an indication of a problem that you can identify right away then. X and z are limited in their use for synthesis, z will allow you to create tri-state buffers and that sort of thing. But in general, sometimes in synthesis these things are ignored. So there are a number of Verilog data types, the ones that are significant for synthesis, which is what we're mostly worried about include wire. A wire represents a signal on a wire that's being driven continuously by some kind of a driver. A reg which as the name implies, synthesizers will a lot of times create a register, but that's not always the case. It's more designed for variables that have some kind of a storage element. Integer and real are similar to what integer real are in C, time is a unique type of data type within Verilog, which is used to represent time. So you can define the units of time, you can define a particular simulation time and on with time variables. Parameter allows you to parametize the design so you can set a parameter, create a vector that's n wide, and then to find what n is later on in the code. So you can alternate between 16 and 32-bit implementations for example, so parameters are very useful. An event is something that happens at a particular point in time that can be used to launch other activities and so on and simulation. So for example a clock edge would be an event in time that would be used to define flip-flops or other registers and so on and synthesis and also a particular point in time within simulation. So we'll talk more about data types in future videos, but we just wanted to give you an idea that there are these different kinds of data types that exist within Verilog. So when you start to write a lot of Verilog code, you want to have a tool that will help you write this code very efficiently. And so you want to have a text editor that has features that are designed for use with Verilog that provide key word highlighting, auto indents, things of that nature. And so this is a list of some editors that people use to create Verilog code that are very useful for that purpose. Some of the free editors include VI, which is popular in the Linux world, EMACS which includes VHDL extensions. So it's very helpful with VHDL, if you want to write VHDL EMAC's a good choice. PSpad which allows keyword highlighting for both either Verilog or VHDL, and Sigasi which supports Verilog, VHDL, and System Verilog. Commercially, there are a number of editors that are fully featured, very powerful. A lot of times project teams will agree to use only one type of editor. So in those cases, you might be using UltraEdit or Multi-Edit or Slick-Edit, etc. So this is kind of a short list, but these are some of the better editors out there available for creating Verilog. I want to mention specifically Sigasi, because it has an additional feature in that it is syntax aware. So it knows Verilog syntax and also VHDL and System Verilog for that matter. So as you're writing the code it will give you instant feedback on errors and it'll give you suggestions for how you might correct those errors. So that helps reduce development time, helps you write better code and so on, because as you're writing the code the syntax errors are removed. You might still have logical errors, it doesn't really address those. But at least the syntax errors could be cleaned up by use of this particular editor. You can download and try it yourself from the URL that's listed here to get the student version, you can also get a commercial version free for 30 days. It's worked really well here, we found it useful, so it will be worth to try. When you use Sigasi, it'll identify where the errors are by the use of red circle with an x in it. And as you hover over that it'll give you suggestions for fixing the error, in this particular case there's some VHDL code, it works on Verilog as well. But in this case, there are several missing key words, missing semicolons, things in that nature. And they're indicated by the x either in the line where the keyword's missing or the line after it. And so then you can look for that and find the errors and correct them as you go. So in summary in this video, you have learned the basics of Verilog syntax. You've also learned a little bit about Verilog variable values and data types. And you've been given a list of possible editors that can be used to create Verilog code, including Sigasi, which is capable of syntax correction on the fly. We'll discuss more and more about Verilog data types, variable types, modules, and so on in future video.
