Welcome to an introduction to Verilog. In this video, you will learn the history of the Verilog HDL language, an approach to learning Verilog, and a first phrase design example done three different ways showing the versatility of Verilog. Verilog which was standardized as IEEE 1364 is a hardware description language used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. In Verilog, a design consists of modules. In addition, most designs import library modules. A simple AND gate in Verilog would look something like the following. So here we see an initial couple of lines of comments, Verilog code lines to begin with a pair of slashes or comments, and do not generate any hardware. This is a module that describes a simple two input NAND gate.The module name is AND gate which is followed by sensitivity list with inputs X1 and X2. The output is f. The assignment statement assign f equals X1 and X2 will cause the synthesizer to create an AND gate in the FPGA. The ampersand indicates that the signals are to be added in a Boolean manner. All modules end with an endmodule statement. So Verilog is an acronym for verifying logic. Verilog is a modeling language created by Gateway Automation in 1984. Gateway is acquired by Cadence in 1990. With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International Organization now known as Accellera. Verilog was later submitted to IEEE and became the IEEE Standard 1364 in 1995, commonly referred to as Verilog-95. Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001, another update occurred in 2005. In many cases, the FPGA vendors are supporting Verilog-2001 may not support 2005 as of yet, and so it's important to know the distinction between these because it may affect how the synthesizer treat your Verilog code. As of 2009, the SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 which is now IEEE Standard 1800-2009. Current version is IEEE Standard 1800-2017. While some FPGA vendors tools support synthesis from SystemVerilog, most of them, in fact all of them will support Verilog, but only some will support SystemVerilog at this point, and the version of SystemVerilog they support is probably a couple of revisions back. It might be still 2009, that's something that you have to check with your FPGA vendor tools as you're working with Verilog as an HDL input. So how can you learn Verilog? It's like any other language. If you are going to learn say Spanish, you at first learn a couple of key phrases, and you practice them, and practice them. So you learn things like where's the bathroom? How much for a beer? Important things that you need to know in order to get around wherever you are and communicate with people in Spanish. In Verilog, you also learn a few key phrases, and then after a while you have a sense of how the language works, and then the next step is to learn the grammar and the syntax so that you can put larger concepts together. You can make compound sentences and things. When you do a similar thing with Verilog, you'll learn how to make smaller constructs, and then bigger constructs as you go, and then of course, you just want to practice, practice, practice until the point comes where your knowledge of the language is become intuitive, and you don't even really have to think about it in order to write Verilog code. So this is an example, our first phrase is a 4-bit comparator. Here what you see is a number of gates that have been combined together. The idea here is that we're going to compare two 4-bit vectors A and B, and to do that we're going to use these XNOR gates here. So this is an XOR gate followed by an inverter which gives you an XNOR gate. The XNOR will be equal to one only if all the inputs are the same, so it's like a 1-bit comparator if you will, and then we're going to combine all four of these comparators together in a NAND gate. If all of them are true that means all the bits match up, one to one, then the equals be true, so this is a typical comparator circuit. So now we want to learn how do we write this, a description of this circuit in Verilog shifts of the synthesizer is going to create this exact circuitry. In general, there are three different ways to model circuits in Verilog. First is a structural modeling in which models are constructed as gates just as they would be in conventional digital circuit design using pre-defined library modules for the gates. Second, we use data flow modeling of the register-transfer level of abstraction or RTL, using concurrent assignment statements. Third, we could use behavioral modeling which uses procedural statements known as an always block similar to process statements in VHDL. Let's apply each of these modeling styles to the comparator example and see what we get. So this is an example of a structural model of a comparator. It uses library modules for the gates inserted into the comparator module. The act of inserting the library modules is known as instantiation. Each instance of the gate model is wired to different signals. The first XNOR gate labeled XNOR zero has A0 and B0 as inputs with AND zero as the output. Each successive XNOR gate instance operates on successive bits of the input vector. The outputs of the XNOR gates are connected to the 4-input AND gate which provides the output. This code will synthesize exactly to the circuit of the comparator just as we saw in the previous slide. This is the data flow model of the comparator. The data flow model provides an output as a function of the input vectors. The description of the comparator in this case is achieved in a single line of code showing the efficiency of this modeling style. It's a lot less typing than structural model, but wIll synthesize to exactly the same circuit. The way to understand the statement is that vectors A and B are XNOR 1-bit at a time. The exponential caret symbol represents the XOR operation in Verilog, and the tilde represents an inverter. The four bits are then added together as represented by the ampersand in front of the parenthetical expression there, and then that gets assigned to the output y. In this particular example, we're using the 1995 syntax for the signal list that's part of the module. So you see the signals A, B and Y are listed with the semicolon after the parentheses there, and then the inputs A and B are defined as 4-bit vectors, and then the output Y is defined. Next we have the behavioral model. In the behavioral model, a special block of code known as the always block is used where in statements are sequential and not concurrent as they are outside of an always block. In an always block statement order matters. So here the output is initialized to zero. Whenever there is a change to A or B, the two vectors are compared, and if equal, the output is changed to a one, otherwise it remains zero. The synthesizer will again create exactly the same comparator circuit based on this description. Although a bit less efficient than a data flow model, this type of modeling can be extended easily to much more complex hardware. So this is the type of modeling that we'll tend to do the most once you become more experienced with Verilog, but the structural modeling and data flow modeling are still used in a lot of examples, so it's good to know how to do all three. So in summary, in this video, you have learned a little bit about the history of the Verilog HDL language from inception in 1984 until the latest IEEE revision in 2017. You've learned an approach to learning Verilog involving assimilation of vocabulary, phrases and syntax, and you've learned a first phrase design example, a comparator that's modeled by the use of either structure, data flow or behavioral descriptions.
