We know that FPGAs are mainly characterised by the presence of three BUILDING BLOCKS: Configurable Logic Block, Input/Output Blocks and Interconnections. We got already familiar with CLBs and IOBs but we need to know more about interconnections. The interconnection resources within an FPGA allow the arbitrary connection of CLBs and IOBs. The main modes of interconnections are DIRECT and SEGMENTED. DIRECT INTERCONNECTION is made of groups of connections that cross the device in all its dimensions. Logic blocks put data on the most suitable channel according to data destination. This implementation usually includes some additional short-range connections that link nearby blocks. SEGMENTED INTERCONNECTION is based on lines that can be interconnected using PROGRAMMABLE SWITCH BOXES. Also in this kind of interconnection there are lines that cross the entire device, in order to maximize the speed of communication and limit signal skew. On one hand, segmented interconnections offer a REDUCED POWER DISSIPATION because resistance and capacity of the interconnection lines are only those of the interconnection length between the blocks. On the other hand the main advantage of direct interconnection is that parasite resistance and capacitance are almost constant, resulting in an IMPROVED PREDICTABILITY OF THE PROPAGATION TIMES OF THE SIGNALS. Therefore, having the RIGHT MIX OF BOTH is going to GUARANTEE us the BEST PERFORMANCE. Let us now consider an example to better clarify how the interconnections are working. The three building blocks presented so far, CLBs, IOBs and INTERCONNECTIONS, interconnect together in the device to create a communication infrastructure composed of the communication lines and IOBs around a bi-dimensional array of CLBs, which covers most of the available die area and represents the true FPGA building block. In this figure we can see a simplified FPGA composed by two times two CLBs structure, eight IO blocks and five switch boxes. Considering that we are focusing on the interconnections, let us now focus just on the five switch boxes. More in details we are interested in knowing the internal structure on a generic switch box SBx. What we are interested in, is in knowing how signals flowing into the interconnecting lines can go from one building block to another one. We know that they can use direct connections, but in our specific case, what we are interested in investigating is in how segmented interconnections can be interconnected by properly configuring the programmable switch boxes. At the end, as the name is suggesting, a PROGRAMMABLE SWITCH BOX, is a box of PROGRAMMABLE SWITCHES. In this figure we are appreciating the boundaries for the switch box represented by the dotted line, while the switch matrices, the interconnection points, have been represented by the green square at the cross of the two lines. As we have done for the switch boxes, let us now see how an switch matrix is realised. A PROGRAMMABLE SWITCH MATRIX is realised by grouping together a set of six PROGRAMMABLE SWITCHES. Each PROGRAMMABLE SWITCH is implemented by using a PASS-TRANSISTOR. In the figure we can see how the six pass-transistors are connected to implement the switch matrix Configuring a programmable switch matrix means that we do have to provide the configuration of the six programmable switches. Within this context, by numbering each of the programmable switches, we can define a sequence of six bit as the configuration of the programmable switch matrix. In our example we started to count from the pass-transistor on the top-left corner. Therefore, a one, zero, zero, zero, zero, zero configuration, is used to enable the pass-transistor on the top-left corner while leaving the other open. This will, as an example, enable a signal to go from the top to the left of the switch matrix. A Zero, one, zero, zero, zero, zero sequence, on the other hand will enable the top-right pass-transistor allowing a signal, as an example, to go from the top to the right of the switch matrix. Following this schema a zero, zero, one, zero, zero, zero is the configuration to enable the bottom-right pass-transistor. To complete the set of for “external” pass-transistors, we can now easily immagine that the zero, zero, zero, one, zero, zero sequence will set the bottom-left pass transistor to enable a signal to go, as an example, from the left to the bottom of the switch matrix. A zero, zero, zero, zero, one, zero configuration will enable a left to right communication. While finally, a zero, zero, zero, zero, zero, one sequence of bits will enable a vertical path for the signal going into this switch matrix.