Dynamic reconfigurable systems are gathering an increasing interest from both the scientific and the industrial world. The need of a comprehensive framework which can guide designers through the whole implementation process is becoming stronger. Just to consider one characteristic of FPGA devices, there are several techniques to exploit partial reconfiguration, but… . Few approaches for frameworks and tools to design dynamically reconfigurable systems . They don’t take into consideration both the hardware and the software side of the final architecture . In general, they cannot be used to design systems for different architectural solutions We know that FPGAs provide large speed-up and power savings – at a price! . Days or weeks to get an initial version working . Multiple optimisation and verification cycles to get high performance Furthermore, these systems are getting incredibly complex. Normal mortals cannot easily program massively parallel systems. This is all turning into an increasing PRODUCTIVITY GAP. Considering the technology improvement and in measuring it, as an example, in number of logic transistors available per chip. We can see that the way in which it is growing it is higher with respect to the productivity in using it. In other words, we are wasting potentialities made available by the chip because we are not able to properly manage them into in our final design. This is definitely wrong! This has to be avoided! That’s a huge field of research right now! This not true only for universities and research centres, but also for companies themselves. As an example: we can see that Xilinx, even if it is a “EE” company, even if they are the one producing the underlying technology at the bases of our systems, they are investing a lot into designing the most advanced and user friendly toolchain! and this is not just something they are doing today, this is part of their culture. Back at the beginning of the century, around 2001-2002, I was a master student, excited about the idea of using FPGAs to implement my runtime adaptive system. It was awesome, I was doing it by writing VHDL code and by using Xilinx Integrated Synthesis Environment, or ISE, to synthesise it and to generate the final bitstream. But I was curious. I was working with an FPGA, the Virtex II Pro, that I knew that it was embedding a Power PC 405 processor… and I was willing of using it, but doing it in pure VHDL, well, it wasn’t easy. Fortunately, I hadn’t to way for too long. That was also the time in which Xilinx was working to the Embedded Development Kit, or EDK. That was huge! That tool changed my design experience. EDK was helping me in creating an embedded system via a graphical user interface just by instantiating the necessary IPs and in connecting them. Well, it wasn’t that easy, but just let me remind it in that way This is a perfect example of a company effort in trying to reduce the productivity gap. Furthermore, once that you have a system based on a processor, you need a toolchain to allow you in getting the best out of the underlying infrastructure, and that was exactly the Xilinx SDK framework. With EDK, and SDK there was also one more interesting news: the release of the Microblaze soft-core. The advent of the Microblaze was terrific. This was opening the doors to a set of completely new research challeges and possibilities. We had all we need to design and prototype multicore systems. And remember, we were around 2005-2006. These tools had improved a lot over the years but there was something new waiting to be included, waiting to be explored, waiting to be used to change everything. High Level Synthesis, also kwon as HLS, can be seen as an automated process to move from an algorithmic description of a desired behaviour to a digital hardware implementation of that behaviour. HLS has been around for a while, early commercial examples developed by Synopsys where already around at the beginning of the '90 but only in the second decade of the twenty first century we can see a real explosion of this technologies. On July 2012 we can read on the Electronic Engineering Times pages “The folks from Xilinx have just made available the first public release of their next generation design environment. The Vivado Design Suite 2012.2 is now available to all ISE Design Suite customers”. This was going to mark an époque. Not only Xilinx was working on including HLS solutions in their frameworks, but ALTERA too with their OpenCL initiative. This was definitely marking the beginning of a new era. Considering the advancements in the FPGA technologies and the increasing interest in coupling them with host solutions to implement complex heterogenous distributed systems, cloud infrastructure, the need for a simplified host integration and an automated infrastructure creation was going to be the next big thing! Xilinx was ready to face this new challenge and they release three new tools: SDSoC, SDNet, SDAccel We are going to here more about them, especially with respect to the SDAccel Development Environment.