In this video, we will discuss some common fabrication processes called CMOS Processes. Cmos stands for Complementary MOS, and complementary means that you have on the same chip both n-channel devices, meaning devices with channels full of electrons when they conduct, and also p-channel devices, which instead have channels that, when conducting they are full of holes. This process is called Local Oxidation of Silicon, or LOCOS. You see here the n-channel device, which we have already discussed, and here you see the p-channel device. Just like the n-channel device has a p-type substrate, the p-channel device has an n-type substrate called the well. This is an n-type well. The source and drain are made of p-type material. And when there is enough negative charge on the gate, then underneath it, it attracts holes, and the holes form a bridge between source and drain. The end well sits on top of the p-substrate, and normally we do not allow positive voltage between p and n. Therefore the p-n junction is not four point bias and it serves as an isolation between the n well body of the p-channel device and the p-substrate. You can see thin oxide regions under the gate here and there. And outside those regions, the oxide becomes thick, like here. And the reason for that is that if you happen to have other structures, for example metal, running across the chip and connecting one device to another, lets say if you had a metal over here uh,sufficiently positive potential on the metal could induce electrons below it, which can interfere with proper polation. But by separating the metal from the substrate by a thick oxide, by all this distance, you avoid this possibility. This characteristic shape of the oxide, as it goes from thick to thin, for example, here is called the bird's beak. This process is rather old. And it has been used for many years in the industry. Today it is used mostly for special purpose processes, for example, for high voltage applications. The standard process today is STI, your Shallow Trench Isolation. And the, the description is similar to what I gave you for the LOCOS process. It's just that the way the thick oxide regions are formed in those so-called transits is different during fabrication, but electrically, electrically the description is similar. A more fancy STI process is the so-called triple well STI. So here you see the n-channel device with its substrate, or body isolated from the common p-substrate of the chip. In this way, these devices can be optimized and also their bodies available separately for each transistor, which can be an advantage for certain types of circuits. Finally, there is a process called SOI, or Silicon on Insulator, where you have a thick hook side separating the devices from the substrate, and the devices themselves are grown on top of this thick hook side. In this class, we will not cover the operation of transistors on SOI processes. So let's look at the device with realistic dimensions. So here is a realistic drawing here. You have the source, you have the drain. Here, you have extensions of the source and the drain. And the reason for these extensions will be clear when we talk about very small dimension effects later on. Then we have the gate, which as I mentioned before, it is taller than what we normally draw it, in this course. And on top of it, you have something called the silicide, which serves to lower the gate resistance. All of this region here is filled with Silicon dioxide, and through that you cut holes, in order to make contact to the source, and the drain. So these two areas are the contacts, and you fill them with metal. This, and the metal makes contact between the source and drain and the wiring which connects your device to other devices on the same chip. For example, this could be the cross section of a wire that runs perpendicular to the surface of the slide. Here is a view of this as you look at it from above. So as you look at from above, you see a rectangle, which the source, another rectangle, which is the drain. And you have metal, this metal here, is, corresponds to this area. And then you have cuts through the zinc oxide which, which serve for you, after you fill them with metal, to make contact between the metal wiring and the underlying and the, and the source underneath. And the same thing happens with the drain. And here, you see the polysilicon gate and on top of it you see the silicide. Finally, here you see some scanning electron microscope images of a mature 45 nano-meter process. The designation 45 nano-meter refers to a certain pitch that is associated with memory design. It does not necessarily mean that the channel is 45 nanometers. Actually, the channel length can be significantly smaller. So here we see a n-channel device. And here you see a p-channel device. This is the gate here. This is the oxide region. It's very thin, and here you see the source and the drain. In similar things happen over here. In addition, you see certain layers. You see like a multilayer structure here. And here, this served to provide strain, mechanical strain to the device, because it has been found that this enhances certain properties, such as mobility. And we will be talking about mobility later on in this course. This slide comes from this source here, with permission by IEEE. So, in this video, we have described very briefly some common, seamless fabrication processes and we have seen some devices with realistic relative dimensions. In the next video, we will start our review of basic semiconductor concepts.