In this video, I will give you a short summary of the so-called Quantum-Mechanical Effects notably including the ones that give rise to Gate Current. Let me begin with Quantum-Mechanical Effects. This is a picture we have seen before. This is the gate region. This is the oxide region here. This is the semiconductor region. So this has been turned 90 degrees from the normal way we draw the transistor. The Fermi potential is fixed and let us consider just the two terminal structure for simplicity. And the variable tension in the bulk is below E sub i, as it befits a pit type region. But the bands bent at near the surface, the firming potential is above E sub i, which is the situation for a end pipe semi-conductor. This is because the surface has been inverted. The electrons of the inversion layer are supposed to be very close to the surface in a very shallow layer. Now, if you have very thin oxides and very high substrate doping, you end up with very high fields and then the bending is very sharp. Now the so-called potential well in which the electrons must find themselves, which is defined by the conduction band edge E sub c, and the oxide wall here becomes very narrow. And because of this, the so called physics of tightly confined particles start becoming evident and you have quantum mechanical effects. Now, it is totally beyond the scope of this course to discuss the nature of such effects. So all I will do is describe those effects have on device characteristics. There are two main effects that take place. One is that the electron density instead of being maximum next to the interface between semiconductor and oxide becomes maximum a little into the semiconductor. In other words, if you pluck electron density per unit volume versus distance away from the interface, you get a maximum which is not right next to the interface but away from it by a distance called d sub m here. This has an effect of increasing your effective oxide thickness. In fact, the increase in oxide thickness is of the same type as we have seen when we discuss depletion. It is equal to this distance d sub m weighted by the ratio of the permittivities of the oxide and the semiconductor. The second effect is that the allowable energy levels split into discrete sub-bands. So rather than having a continuum of energy levels that are allowed in the conduction band, right here where inversion layer takes Occurs. You have certain energy levels above Ec that can no longer be occupied. This effect is similar to increasing the energy gap between the valance band and the conduction band. If the gap increases, you can expect to have a lower n sub i, the intrinsic carrier concentration. And if you go back to the formula for Fermi potential, this means a higher phi sub F, a higher Fermi potential. Because of this, you need a larger surface potential to have inversion. Effectively then, instead of having a surface potential phi sub 0 In strong inversion, you have phi subzero glass, and amount in delta phi sub-zero and the net effect is you have a larger threshold voltage. So, phi sub-m, the distance of the peak of the inversal of the density of the interface and delta sub zero the increase in the potential can impressively be calculated, but you need Poisson's equation and Schrodinger's equation. It is an involved calculation. Some results, not proofs, are given in the text if you're interested. The result is this. Because you have an increase of the effective oxide thickness you have a decrease in the capacitance of, the CV curve goes down as you can see here, here, and there. And the total capacitance in inversion is less than you would have otherwise. And in addition because V0 now became V0 plus delta V0 and the threshold has increased, there is a shift of curve to the right. These are the main effects of the quantum mechanical effects I just described. We now go to another quantum mechanical effect which causes DC gate current which is a major headache. Here is an old device with a thicker sign. We assume polositical gate, so you can define a balance conduction band, both in the gate and the semiconductor. The bands as we show that are already bent in the semiconductor and the inversion layer is very close to the interface. And this dot here indicates one electron being there, just schematically. The oxide also has a conduction band though it is much higher than the other conduction bands. So this electron can not go to the gate because it will have to have enough energy to overpower. This very large energy barrier. Now if you have very thin oxides it turns out that quantum mechanics says that you can through an energy barrier without really having that much energy as required by that energy barrier. For example, an electron can find its way from the inversolier into the oxide above it's conduction band here, and this is called Fowler Nordheim tunneling. Normally, this effect is small. But there's another effect which says that an electron can find itself from the immersion layer to the other side of the oxide without having to go over the barrier like this, and this is the main form of tunneling that worries us, it's called direct tunneling, and it is dominant for very thin oxides. Thinner than three or four nanometers, which in fact is not very thin by today's standards. So this effect started being a problem several years back. The direct tunneling current increases drastically for thinner and thinner oxides. In fact, half a nanometer of change in the oxide thickness can result in a current that is 100 times larger. And I'm talking about the gate current that is possible because of the direct tunneling here. We will later see a set of curves that show this. By the way, holes can tunnel too in the same fashion. So the effect of direct tunneling is a current through the oxide which manifests itself as the gate current. So here I show ou a transistor with a thin oxide. There is tunneling current that goes from the gate to the channel, effectively electrons negatively charged go from the channel to the gate, that's the equivalent of positive current going from the gate to the channel. And part of that current ends up going to the source and part of it goes to the gate. There is also tunneling between the gate and the end source through this thin oxide. Over the so-called overlap region between the gate and the source. And this is called I GS OV. And of course one near the gate we have I GD OV. So the gate current is the sum of all of these currents. Also you can have direct tunneling from the substrate to the gate, especially if the gate is negatively charged, and all of these currents contribute to a gate current that in some cases can be significant and it can interfere with proper device operation. Now the gate to channel current, this current here that is separated into Igs and Igd is proportional to the inversion layer charge, not very surprisingly. And also proportional to the tunneling probability at position x in the channel. The total gate channel current, which will be the sum of IGS plus IGD, can be found if you take the density of the current, which is what this is here, it's the density it's the current per unit area of the gate and you integrate it by multiplying by W dx, which is an element of the gate area and integrating over all the gate area. This is equivalent to taking W outside the integral and integrating from 0 to L. Now some of this current will go towards the gate, and some of it goes towards the source. And it is not very surprising that the closer X is towards the drain, the more that current goes towards the drain. And the closer you are towards the source, the more the corresponding tunnel and current can be Seem to go towards the source. And it turns out that you can actually find those two currents in this way. Let's talk about IGD. The density of the current is weighted by x over L, and the larger of the axis, the larger this weighting factor. So a larger and larger portion of the current density Is associated with a drain. The opposite happens over here. The smaller the x is, the larger this factor becomes so the closer you are to the source the more the corresponding density of the current is associated with the source. So now you can plot the current versus VDS and it turns out if you go through this calculation, which actually is involved, you'll find IGS and IGD go like this. IGD is less than IGS because as you increase VDS, you increase the drained potential. So, the gate to drain potential, which is the potential across the oxide becomes less and less. It is less than the gate to source potential, which is the potential across the oxide over here. So that's why GD is less than IGS. Let us now look at the low noise transistor under a variety of biases. And consider its gate current. Here you see a plot of the absolute value of a gate current versus VGS for two different values of VGS. Because this X axis is logarithmic, we cannot show negative current values on it, so what you see here is only the absolute value of the gate current. But we distinguish two branches for each of these curves, for example, this branch here. Is labeled as being for positive current, and the corresponding branch here is the absolute value of what actually is a negative current, and similarly for the other current. So let us first concentrate on VDS equals zero, for which we get this curve. Now if we have large values of VGS we have an inverted channel and the electrons tunnel form channel to gate, they are negatively charged but we said before this corresponds to a positive current from the gate to the channel and this takes place through four paths, Igs, Igd, Igs overlap and Igd overlap, and the higher the value of Vgs, the more the tunneling current becomes. Not let us instead consider very negative values of VGS. If the value of VGS is sufficiently negative, then here you don't have inversion, but you have accumulation. Now the gate is more negative than the surface and therefore, the electrons tunnel from gate to the bulk of the semiconductor. So this then becomes a current in this direction of negatively charged electrons, which means it is a negative current. This is why this current actually shows negative currents, it shows the absolute value but actually you have negative currents. Now somewhere in between the negative current region and the positive current reason, the two cancel each other out. And this curve goes to minus infinity, indicating on the log axis that the current becomes zero. Now, if instead you have a positive drain voltage, VDS, then let's take 1 case where VGS is equal to 0 and VDS is equal to 1 corresponds to this point which shows a negative current. Why is the current negative? Because if the drain is positive, more positive than the gate then you have tunneling of electrons from the gate. To the drain, which corresponds to a negative current through this overlap region, that's why this is shown as negative. Eventually of course, if Vgs becomes high enough, you end up with current similar to those that you have before, and some were in between, there is cancellation, so if we had enough resolution you would see this going all the way down as the other current did. Let us now take a look at the current per unit of gate area. This is the current density nms per square centimeter. Each of these curves is similar to one of this curve, but the barometer here is the oxide thickness. So we start with a rather thick oxide by modern standards, 2.1 nm. Go 1.9, 1.7, 1.5, and 1.3. You can see clearly here the drastic increase of current density as you make the oxide thinner and thinner. So, for example, if you decrease the oxide thickness from 1.7 to 1.5, which is only 0.2 nanometers, or 2 angstroms, you see that the current goes up by more than an order of magnitude. And of course it quickly goes out of hand. Once you try to decrease the thickness even more. So we can not make the oxide extremely thin. On the other hand, we would like to have a thin oxide, because that gives us a large oxide combustance per unit area. C ox prime and as you can recall C ox prime is a constant. It's one of the quantities in the constant of proportionality in any current equation of the device for example, IDS is W over L times u(greek letter) times C ox Prime times a bunch of other terms. So you would like to have a large CX prime in order to have a large car, and for a given gate drive. On the other hand, you cannot arbitrarily increase CX prime by making the oxide thinner because of the tunneling problems, as we have already mentioned. So another possibility to increase C ox prime is to keep the oxide thicker, but make its permittivity large. So use a different type of insulating material that has a high k, k meaning a high dielectric constant, which would give you a large permittivity and it would allow you to obtain a large oxide capacitance per unit area without having to go to very thin oxides. In the next video, we will talk about another form of leakage current that has to do with junctions.
