So far, we have shown a simple model for operation up to medium frequencies, and we will be more specific what this means later on. The model included five capacitances, which were determined by varying certain voltages and looking at certain charges, but there are more than five possible combinations of voltages and charges in the device. In this video, we will consider all possible combinations which will result in 16 different parameters, and then we will show that some of them are dependent on others, and we will end up with a set of 9 independent capacitance parameters that forms a complete set. Let us begin with a transistor, assume to be only the intrinsic part with four voltages from each terminal to ground, and these voltages in general can be varying. The variations in general can be large, but, in the present discussion, we are concentrating on small signal variations, which implies that every one of these voltages can contain a small variation. For example, the gate voltage contains a small variation denoted by small v small g, and a possibly large bias voltage, VG. The same for all of the other elements, so the battery symbols stand for the DC values of the terminal voltages with respect to ground, and the round voltage sources stand for small signals that are superimposed on top of those DC voltages. Let us take one of the currents, for example, the drain current. It consists of a DC component capital I capital D, plus a small signal components, small i small d, and you will recall that this small signal component consists of a transport current and the charging component. For now, we will be concentrating on the charging components of the currents. The charging component of the drain current was denoted by ida, and, as you may remember, it is given by the derivative of the drain charts with respect to time, but because the drain charts in general depends on all four voltages, Vd, Vs, Vg, and Vb, when we take this partial derivative, we need to consider those independences. We end up with this equation here. This is the charging component of the drained current, and, from the chained rule of differentiation, we get dq dv dv dt. That will give you how the charging component of the drain current varies when the drain voltage varies, assuming the other voltages are held constant. Then to add, we have added the corresponding component that has to do with a gate voltage, dqD, dvG, dvGd, and so on. So, for each of these charging currents, for each terminal, we end up with a similar equation. This is the corresponding equation for the gate current, the corresponding equation for the body current, and the corresponding equation for the charging component of the source current. Now, we will define some capacitance parameters. Because each of the partial derivatives in these four equations is of the form dq dv, it has units of charge over voltage, which, of course, gives you capacitance, and we will define Ckk. This is capacitance corresponding to terminal k, if you vary that voltage at that terminal, and you look at the charge that enters that terminal. If the subscripts are different, for example, Ckl, core l is different from k, we do the same thing, but we introduce a minus sign. The reason for the minus sign has been explained when we first introduced capacitance, so please go back to that lecture if you do not understand the meaning of the minus sign. Now, replacing these partial derivatives of the form DQ DV by the corresponding capacitances, these four equations become like this. I repeat here the definition of the capacitances. The equations become like this. Okay, in general, you can expect that CXY will be different from CYX. For example, there is no reason to assume that CDG, the drain gate capacitance parameter, will be equal to CGD, the gate drain capacitance parameter. Each of them is defined by separate partial derivative, and it so happens that these two partial derivatives gives you different answers in general, so you cannot work that these two will be different. This may sound strange at first. Let us please leave it at that for a moment. Don't associate anything with the plate capacitor, then we'll come back to this problem, but, in general, again, Cxy can be expected to be different than Cyx. Now, the sum of all four currents, all charging currents entering the device, as we have seen before is equal to zero, which means that, if you know three of these carbons, you know the fourth through this equation. Therefore, we only need three of these equations and we can neglect the fourth. We choose to neglect the source carbon, and we end up with a set of three equations giving you the drain charging component, the gate charging component, and the body charging component. Here is, again, the drain charging component from the previous set of equations, and I would like now to discuss certain properties that hold for these capacitors. I will do so by taking two special cases. The first case I will consider is the case where all of the small signal voltages are equal, and their common value will be denoted by v. This corresponds to this situation. You can see that each terminal voltage, for example, the gate voltage, has a DC term Vg plus small signal voltage term v(t). The short voltage has DC term Vs plus the same small signal voltage v(t). So you can see that all of the four terminals small signal voltages are equal to v(t). [COUGH] Therefore, these derivative's now in the top equation can be replaced by dv, dt, and we pull dv, dt as a common factor, and we get this equation. However, this should be expected to give you 0. This is the charging component of the drain current, but, if you look here, nothing is varying as far as terminal to terminal voltages are concerned. Right, because, for example, the gate to source voltage is vg minus vs, which is a DC quantity. The drain to source voltage is vd minus vs, again a DC quantity. Here you have a transistor with all terminal to terminal voltages fixed. Therefore, the drain current is fixed. Nothing is changing, and nothing is charging, so you can expect that the corresponding charging component will be equal to zero, and because this equation must hold for all dividities, the only possible conclusion is that what is in the parentheses here must be equal to zero, from which you get this relation. That Cdd is equal to Cdg plus Cdb plus Cds. Now we'll take a second case. Again, I start with the same equation. This is the gate equation, the body current equation, and the source charging component equation, and I will take the special case in which only the drain voltage is changing and all of the other voltages are fixed. So VG, VB and VS are not changing, and, therefore, the derivative with respect to time is zero. So all of these terms here will be equal to zero, and the only terms that will be non-zero are the ones corresponding to the first part here. In other words, the drain charging current is this. This is the gate current, body current, and the short charging component. This is all we have. The rest is zero, but now we know that the sum of all of these currents is equal to zero. We know this. So if you add these four, and you pull out dvd/dt as a common factor, we get that this is equal to 0, and because this equation must be true for all values of dv/dt, it means that what multiplies dv dt must be equal to 0, from which we get this result. Now you can do exactly the same thing with the other capacitances, and you end up with the following general properties. This is the first, we have already proven this. This was proven from the first property I showed you, this from the second. The same holds for Cgg, or rather the corresponding relation calls for Cgg, for Cbb and for Css. So now we begin to see that, although we were able to define many different capacitance parameters, not all of them are independent. There is a relation between them, and that will allow us to reduce the number of capacitances we need to fully describe the capacitance behavior of the MOS transistor. We will have use for these relations shortly. Here we are again. These are the three currents. I remind you that we said we're going to neglect the source current because, if we know these three currents, the fourth current can be found from the fact that the sum of all four currents must be equal to zero, so we concentrate on these. I remind you that Cdd was just a sum of Cdg, Cdb, and Cds. Correspondingly, Cgg over here was found to be this, and Cbb over here was found to be this. Although in these equations, it seems that we have 1, 2, 3, 4 times 3, 12 different parameters, three of those can be expressed in terms of the others. So instead of 12, we have 9 independence capacitance parameters. That means that the maximum number of capacitance parameters we need to fully describe the transistor in quasi static operation is nine. We will use this fact, and, in the next video, we will talk about how to derive a complete quasi static model using nine capacitance parameters.
